1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device provided with a semiconductor memory unit having memory elements integrated therein and a decoder circuit for selecting the memory elements.
2. Description of the Related Art
Decoder circuits for selecting memory elements in semiconductor memory devices receive address lines or predecode lines transmitting signals represented by combination of addresses and select word lines connected to the memory elements. Therefore, an increase in the operating speed of a decoder circuit will result in an increase in the operating speed of a semiconductor memory device.
However, in a decoder circuit receiving pulse signals, which are suitable for increasing operating speed, it is necessary to charge/discharge a signal line for each address cycle (see for example, Japanese Unexamined Patent Application Publication No. H11-102586). Therefore, current consumption in the decoder circuit increases with increasing operating speed.
On the other hand, Japanese Unexamined Patent Application Publication No. H7-73674 describes a decoder circuit which receives a data-type signal having logic states for which charging or discharging is performed only once in a cycle. In such a decoder circuit, setting the logic state of a data signal to a selection state before the logic states of the other data signals fully become non-selection states will cause multiple selection. This results in a decrease in the operating speed of the decoder circuit since it is necessary to control the timing for shifting from the selection state of a data signal to the selection state of another data signal.
Thus, such known techniques described above have disadvantages of an increase in current consumption due to frequent charge/discharge of signal lines and a decrease in the operating speed due to selection operations of word lines.